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STV0119A
PAL/NTSC HIGH PERFORMANCE DIGITAL ENCODER
. . . . . . . . . . . . . . . .
NTSC-M, PAL-B, D, G, H, I, N, M, PLUS NTSC-4.43 ENCODING (OPTIONAL PEDESTAL IN ALL STANDARDS) SMALL AND ECONOMICAL SO28 PACKAGE LINE SKIP/INSERT CAPABILITY SUPPRESSING THE NEED FOR AN EXTERNAL VCXO, THUS REDUCING APPLICATION COST 4 SIMULTANEOUS ANALOG OUTPUTS : RGB + CVBS, or S-VHS (Y/C) + CVBS1 + CVBS2 MACROVISIONTM REV7.01/REV6.1 COPY PROTECTION PROCESS IN BOTH NTSC AND PAL 54MHz INPUT MULTIPLEX INTERFACE FOR DOUBLE ENCODING APPLICATIONS (TO BE ABLE TO ENCODE OR NOT THE OSD CONTENT OF THE VIDEO INPUT STREAM) CROSS-COLOR REDUCTION BY SPECIFIC TRAP FILTERING ON LUMA WITHIN CVBS FLOW CLOSED CAPTIONING, CGMS ENCODING AND TELETEXT ENCODING
. . . . . . . . .
CHROMINANCE FILTERING WITH 4X OVERSAMPLING TO EITHER 1.1MHz, 1.3MHz, 1.6MHz or 1.9MHz WIDE CHROMINANCE BANDWIDTH FOR RGB ENCODING (2.45MHz) 24-BIT DIRECT DIGITAL FREQUENCY SYNTHESIZERFOR COLOR SUBCARRIER PROGRAMMABLE RESET OF COLOR SUBCARRIER PHASE (4 MODES) EASY CONTROL VIA FAST I 2C BUS TWO I2C ADDRESSES AUTOTEST OPERATION MODE (ON-CHIP COLOR BAR PATTERN 100/0/75/0) CMOS TECHNOLOGY WITH 3.3V POWER SUPPLY APPLICATIONS : SATELLITE, CABLE & TERRESTRIAL DIGITAL TV DECODERS, MULTIMEDIATERMINALS, DVD PLAYERS
ITU-R/CCIR601 ENCODING WITH EASILY PROGRAMMABLE COLOR SUB-CARRIER FREQUENCIES DIGITAL FRAME SYNC INPUT/OUTPUT (ODDEVEN/VSYNC), PROGRAMMABLE POLARITY AND RELATIVE POSITION DIGITAL HORIZONTAL SYNC INPUT/OUPUT (HSYNC), PROGRAMMABLE POLARITY AND RELATIVE POSITION DIGITAL LINE OR FRAME SYNC EXTRACTION FROM ITU-R/CCIR656 / D1 DATA MASTER OPERATION MODE, PLUS 6 SLAVE MODES INTERLACED/NON-INTERLACED OPERATION MODES FULL OR PARTIAL VERTICAL BLANKING LUMA FILTERING WITH 2X OVERSAMPLING & SINY/Y CORRECTION
SO28 (Plastic Micropackage) ORDER CODE : STV0119A
Note : This device is protected by US patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. The use of MacrovisionTM's copy protection technology in the device must be authorized by MacrovisionTM and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by MacrovisionTM. Reverse engineering or disassembly is prohibited. Please contact your nearest STMicroelectronics sales office for more information.
June 1998
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STV0119A CONTENTS
I II II.1 II.2 III IV IV.1 IV.2 IV.3 IV.4 IV.5 IV.5.1 IV.5.2 IV.5.3 IV.6 IV.7 IV.8 IV.9 IV.10 IV.11 IV.12 IV.13 IV.14 IV.15 IV.15.1 IV.15.2 IV.15.3 IV.15.4 IV.16 IV.17 IV.18 IV.19 IV.20 V V.1 V.2 V.3 V.4 VI VI.1 VI.2 VII VIII
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Page
3 3 3 4 5 6 6 6 10 11 12 12 13 14 15 15 16 16 17 17 18 18 19 19 19 19 20 20 21 22 24 24 24 25 25 25 25 26 27 27 28 41 42
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN CONNECTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DATA INPUT FORMAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIDEO TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLAVE MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization onto a Line Sync Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization onto a Frame Sync Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization onto Data-embedded Sync Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . INPUT DEMULTIPLEXER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUB-CARRIER GENERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BURST INSERTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LUMINANCE ENCODING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHROMINANCE ENCODING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMPOSITE VIDEO SIGNAL GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RGB ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLOSED CAPTIONING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGMS ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TELETEXT ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signals Exchanged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmission Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Teletext Pulse Shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DUAL ENCODING APPLICATION WITH 54MBIT/S YCRCB INTERFACE . . . . . . . . . . LINE SKIP / LINE INSERT CAPABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MACROVISIONTM COPY PROTECTION PROCESS REV7.01/6.1 . . . . . . . . . . . . . . . . CVBS, S-VHS AND RGB ANALOG OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC ELECTRICAL CHARARCTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER CONTENTS AND DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STV0119A
REVISION HISTORY
October 1996 February 1997
: :
Advance Data Preliminary Data Main Modifications : - to get direct connection to SCART in Y/C mode, R and G signals have been moved as G/Y on Pin 20 and R/C on Pin 19. - RGB levels have been rescaled for compatibility between CVBS/Y-C and RGB levels with only one value of IREF(R GB). - revision ID is now 02 hexa (register 18 dec). Update of characteristics (DC and AC electrical characteristics). Revision ID unchanged. Improvement of luminance filtering in case of OSD input data. Revision ID is now 03 hexa (register 18 dec). New sale type : STV0119A. Adjonctions of missing information on AC characteristics for Teletext signals.
May 1997 November 1997
: :
June 1998
:
I - GENERAL DESCRIPTION The STV0119A is a high performance PAL/NTSC digital encoder in a low cost package. It converts a 4:2:2 digital video stream into a standard analog baseband PAL/NTSC signal and into RGB analog components. The STV0119A can handle interlaced mode (with 525/625 line standards) and non-interlaced mode. It can perform Closed-Captions, CGMS or Teletext encoding and allows MacrovisionTM 7.01/6.1 copy II - PIN INFORMATION II.1 - Pin Connections
HSYNC YCRCB7 YCRCB6 YCRCB5 YCRCB4 YCRCB3 YCRCB2 YCRCB1 YCRCB0 VSS CVBS VR_CVBS IREF(CVBS) VSSA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSYNC/ODDEVEN SDA SCL RESET CKREF TTXD TTXS/CSI2C VDD G/Y R/C B/CVBS VR_RGB
0119A-01.EPS
protection. Four analog output pins are available, on which it is possible to output either S-VHS(Y/C) + CVBS1 + CVBS2 or RGB + CVBS. Moreover, it is possible to use two STV0119A in parallel to interface with ST's MPEG decoder ICs that are able to deliver a 54Mbit/s "double" YCrCb stream (e.g. the STi3520M). This allows for example to encode OSD in one of the streams only.
IREF(RGB) VDDA
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STV0119A
II - PIN INFORMATION (continued) II.2 - Pin Description
Pin 1 Name HSYNC Type I/O Function Line Synchronization Signal : - Input in ODDEVEN+HSYNC or VSYNC + HSYNC or VSYNC slave modes - Output in all other modes (master/slave) - Synchronous to rising edge of CKREF - Default polarity : negative pulse Input : time multiplexed 4:2:2 luminance and chrominance data as defined in ITU-R Rec601-2 and Rec656 (except for TTL input levels). This bus interfaces with MPEG video decoder output port and typically carries a stream of Cb,Y,Cr,Y digital video at CKREF frequency, clocked on the rising edge (by default) of CKREF. A 54-Mbit/s `double' Cb, Y, Cr, Y input multiplex is supported for double encoding application (rising and falling edge of CKREF are operating). Output: for test purpose only.
2 3 4 5 6 7 8 9 10 11
YCrCb7 YCrCb6 YCrCb5 YCrCb4 YCrCb3 YCrCb2 YCrCb1 YCrCb0 VSS CVBS
I/O I/O I/O I/O I/O I/O I/O I/O Supply Output
Digital Ground Analog Composite Video Output (current-driven). CVBS must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended CVBS amplitude is proportional to IREF(CVBS) (VOUT(N) = N x R LOAD x IREF(CVBS)/96) with N = [0511] VOUT(Max.) = 1VPP and IOUT(Max.) = 5mA Internal Reference Voltage for the 9-bit DAC CVBS. VR_CVBS must be connected to analog ground over a capacitor (6.8nF typ.), VR_CVBS = 1.9V Reference current source for the 9-bit DAC CVBS. - IREF(CVBS) must be biased to analog ground over a reference resistor RREF(CVBS) - RREF(CVBS)(Min.) = 5.95 x R LOAD/VOUT(Max.) with VOUT(Max.) = 1VPP and IOUT(Max.) = 5mA (IREF(CVBS) = VREF(CVBS) /RREF(CVBS) ), VREF(CVBS) (Typ.) = 1.12V. Analog ground for DACs Analog positive power supply for DACs (+3.3V nom.) Reference current source for Tri-DAC R/Y,G/C,B/CVBS. -IREF(RGB) must be connected to analog ground over a reference resistor RREF(RGB) -RREF(RGB)(Min.) = 5.95 x R LOAD/VOUT(Max.), with VOUT(Max.) = 1VPP and IOUT(Max.) = 5mA (IREF(RGB) = VREF(RGB)/RREF(RGB) ), VREF(RGB) (Typ.) = 1.12V. Internal reference voltage for the 9bit Tri-DAC R/Y,G/C,B/CVBS. VR_RGB must be biased to analog ground over a typical 6.8nF capacitor, VR_RGB = 1.9V. Analog `Blue' or CVBS output (current-driven). This output must be connected to analog ground over a load resistor (R LOAD). Following the load resistor, a simple analog low pass filter is recommended. VOUT(Max.) = 1VPP and IOUT(Max.) = 5mA (VOUT(N) = N x RLOAD x IREF(RGB) /96) with N = [0-511]. Analog `Red' or S-VHS Chrominance output (current-driven). This output must be connected to analog ground over a load resistor (R LOAD). Following the load resistor, a simple analog low pass filter is recommended. VOUT(Max.) = 1VPP and IOUT(Max.) = 5mA (VOUT(N) = N x RLOAD x IREF(RGB) /96) with N = [0-511]. Analog `Green' or S-VHS Luminance output (current-driven). This output must be connected to analog ground over a load resistor (R LOAD). Following the load resistor, a simple analog low pass filter is recommended. VOUT(Max.) = 1VPP and IOUT(Max.) = 5mA (VOUT(N) = N x RLOAD x IREF(RGB) /96) with N = [0-511]. Digital positive supply voltage (+3.3V nom.) Output : positive sync pulse for control of Teletext buffer in external demultiplexer or Transport IC. Teletext data stream from external demultiplexer or Transport IC synchronous to rising edge of CKREF signal average rate of 6.9375Mbit/s. Output in test mode only.
12
VR_CVBS
I/O
13
IREF(CVBS)
I/O
14 15 16
VSSA VDDA IREF(RGB)
Supply Supply I/O
17 18
VR_RGB B/CVBS
I/O O
19
R/C
O
20
G/Y
O
21 22 23
VDD TTXS/CSI2C TTXD
Supply I/O I/O
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STV0119A
II - PIN INFORMATION (continued) II.2 - Pin Description (continued)
Pin 24 Name CKREF Type I Function Master clock reference signal. Its rising edge is the default reference for set-up and hold times of all inputs, and for propagation delay of all outputs (except for SDA output). CKREF nominal frequency is 27MHz (CCIR601) : input pad with pull down (50k Typ.) Hardware reset, active LOW. It has priority over software reset. NRESET imposes default states (see Register Contents). Minimum Low level required duration is 5 CKREF periods : input pad with pull down (50k Typ.) I2C bus clock line (internal 5-bit majority logic with CKREF for reference) : input pad with pull down (50k Typ.) I2C bus serial data line. Input : internal 5-bit majority logic with CKREF for reference Output : open drain Frame sync signal : - input in slave modes, except when sync is extracted from YCrCb data - output in master mode and when sync is extracted from YCrCb data - synchronous to rising edge of CKREF - ODDEVEN default polarity : odd (not-top) field : LOW level even (bottom) field : HIGH level
25
RESET
I
26 27
SCL SDA
I I/O
28
VSYNC/ ODDEVEN
I/O
III - BLOCK DIAGRAM
TTXD 23 TTXS/ CSI2C 22 CSI2C TTXS TELETEXT VDD 21 YCRCB7 2 YCRCB6 3 DEMULTIPLEXER 9-BIT TRIDAC LUMA PROCESSING TRAP MACROVISION 7.0.1 / 6.1 CLOSED CAPTIONS CGMS VSSA CHROMA PROCESSOR VDDA 14 VSSA 15 VDDA 11 CVBS SYNC CONTROL & VIDEO TIMING GENERATOR CSI2C CTRL + CFG REGISTER 9-BIT DAC VSSA
0119A-02.EPS
STV0119A
AUTOTEST COLOR BAR PATTERN VDDA 20 G/Y RGB ENCODING 19 R/C SWITCH 18 B/CVBS 17 VR_RGB 16 IREF(RGB)
CB-CR
YCRCB5 4 YCRCB4 5 YCRCB3 6 YCRCB2 7 YCRCB1 8 YCRCB0 9 VSS 10
Y
VSYNC/ODDEVEN 28 HSYNC 1 RESET 25 CKREF 24 27 SDA 26 SCL
12 VR_CVBS 13 IREF(CVBS)
I2 C BUS
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STV0119A
IV - FUNCTIONAL DESCRIPTION The STV0119Acan operate either in master mode, where it supplies all sync signals, or in 6 slave modes, where it locks onto incoming sync signals. The main functions are controlled by a micro-controller via an I2C 2-wire bus. Refer to the "User's Register Description" for an exhaustive list of the control possibilities available. IV.1 - Data Input Format The digital input is a time-multiplexed ITU-R656 /D1-type [Cb, Y, Cr, Y] 8-bit stream. Note that "ITU-R" was formerly known as "CCIR". Input sam ples are latched in on the rising edge (by default) of the clock signal CKREF, whose nominal frequency is 27MHz. Figure 1 illustrates the expected data input format. Alternatively, a 54-Mbit/s stream can be fed to the STV0119A,refer to Section IV.17 ("dual encoding") for details. The STV0119A is able to encode interlaced and non-interlaced video. One bit is sufficient to automatically direct the STV0119A to process non-interlaced video. Update is performed internally on the first frame sync active edge following the programing of this bit. The non-interlaced mode is a 624/2 = 312 line mode or a 524/2 = 262 line mode, where all fields are identical. An `autotest' mode is available by setting 3 bits (sync[2:0]) within the configurations register0. In this mode, a color bar pattern is produced, independentlyfrom video input, in the adequate standard. As this mode sets the STV0119A in master mode, VSYNC/ODDEVEN and HSYNC pins are then in output mode. IV.2 - Video Timing The STV0119A outputs interlaced or non-interlaced video in PAL-B, D, G, H, I, PAL-N, PAL-M or NTSC-M standards and `NTSC- 4.43' is also possible. The 4-frame (for PAL) or 2 frame (for NTSC) burst sequences are internally generated, subcarrier generation being performed numerically with CKREF as reference. Rise and fall times of synchronizationtips and burst enveloppeare internally controlled according to the relevant ITU-R and SMPTE recommendations. Figures 2 to 7 depict typical VBI waveforms. It is possible to allow encoding of incoming YCrCb data on those lines of the VBI that do not bear line sync pulses or pre/post-equalisation pulses (see Figures 2 to 7). This mode of operation is refered to as "partial blanking" and is the default set-up. It allows to keep in the encoded waveform any VBI data present in digitized form in the incoming YCrCb stream (e.g. WSS data, VPS, supplementary Closed-Captions line or StarSight data, etc.). Alternatively,the complete VBI may be blanked(no incoming YCrCb data encoded on these lines, "full blanking"). The complete VBI comprises of the following lines : - for 525/60 systems (SMPTE line numbering convention) : lines 1 to 19 and second half of line 263 to line 282. - for 625/50 systems (CCIR line numbering convention) : second half of line 623 to line 22 and lines 311 to 335. The `partial' VBI consists of : - for 525/60 systems (SMPTE line numbering convention) : lines 1 to 9 and second half of line 263 to line 272. - for 625/50 systems (CCIR line numbering convention) : secondhalf of line 623 to line 5 and lines 311 to 318. Full or partialblanking is controlledby configuration bit `blkli in configuration register1'. Note that : - line 282 in 525/60/SMPTEsystems is either fully blanked or fully active. - line 23 in 625/60/CCIR systems is always fully active. In an ITU-R656-compliant digitalTV line, the active portion of the digital line is the portion included between the SAV (Start of Active Video) and EAV (End of Active Video) words. However, this digital active line starts somewhat earlier and may end slightly later than the active line usually defined by analog standards. The STV0119A allows two approaches : - It is possible to encode the full digital line (720 pixels / 1440clock cycles). In this case, the output waveform will reflect the full YCrCb stream included between SAV and EAV. - Alternatively, it is possible to drop some YCrCb samples at the extremities of the digital line so that the encoded analog line fits within the `analog' ITU-R/SMPTE specifications. Selection between these two modes of operation is performed with bit `aline' in configuration register 4. In all cases, the transitions between horizontal blanking and active video are shaped to avoid too steep edges within the active video. Figure 8 gives timings concerning the horizontal blanking interval and the active video interval.
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STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) Figure 1 : Input Data Format
4T E A V 276T Digital Standing Interval 1716T Line Duration
0119A-08.EPS
4T S A V 1440T Digital Active Line E A V
NTSC, PAL M (525 Line / 60Hz)
288T
PAL B, D, G, H, I, N (625 Line / 50Hz)
1440T 1728T
Figure 2 : PAL-BDGHI, PAL-N Typical VBI Waveform, Interlaced Mode (CCIR-625 Line Numbering)
0V IV A B
308
309
310
311
312
313
314
315 Full VBI1
316
317
318
319 A
320
Partial VBI1 I
621
622
623
624
625
1
2 Partial VBI2 II
3 Full VBI2
4
5
6 A
7
22
23
308
309
310
311
312
313
314
315
316
317
318 A
317
335 B
336
III
621
622
623
624
625
1
2 I II
3
4
5
6
7
8
C III IV Frame synchronization reference 0V : I, II, III, IV : 1st and 5th, 2nd and 6th, 3rd and 7th, 4th and 8th fields A: Burst phase : nominal value +135 B: Burst phase : nominal value -135 C: Burst suppression internal
Figure 3 : PAL-BDGHI, PAL-N Typical VBI Waveform, Non-interlaced Mode ("CCIR-like" Line Numbering)
Full VBI Partial VBI 0V A B
308 309 310 Burst phase toggles every line
311
312
1
2
3
4
5
6
7
8
22
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0119A-10.EPS
0119A-09.EPS
STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) Figure 4 : NTSC-M Typical VBI Waveforms, Interlaced Mode (SMPTE-525 Line Numbering)
Full VBI1 Partial VBI1 1 2 3 4 5 6 7 8 9 10 18 19
H
H Full VBI2 Partial VBI2
0.5H
H
262
263
264
265
266
267
268
269
270
271
272
273
282
0.5H VBI3 525 1 2 3 4 5 6 7 8
H
H
9
10
18
19
VBI4
0119A-11.EPS
263
264
265
266
267
268
269
270
271
272
273
282
Figure 5 : NTSC-M Typical VBI Waveforms, Non-interlaced Mode ("SMPTE-like" Line Numbering)
Full VBI Partial VBI 3H 262 1 2 3 4 3H 5 6 7 3H 8 9 10 18 19
0119A-12.EPS
H
H
H
0.5H
H
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STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) Figure 6 : PAL-M Typical VBI Waveforms, Interlaced Mode (CCIR-525 Line Numbering)
F' F F' F 0V Full VBI1 Partial VBI1 I A B
519 F
520 F'
521 F
522
523
524
525
1
2 Partial VBI2 II
3 Full VBI2
4
5
6
7
8 A
9
16 B
17
257 F F'
258 F
259
260
261
262
263
264
265
266
267
268
269
270 A
271 279 B
280
III
519 F'
520 F
521
522
523
524
525
1
2
3
4
5
6
7 A
8 B
9
IV
257
258
259
260
261
262
263
264 I II
265
266
267
268
269
270
271
272
C III IV
0V : I, II, III, IV : A: B: C:
Frame synchronizationreference 1st and 5th, 2nd and 6th, 3rd and 7th, 4th and 8th fields Burst phase : nominalvalue +135 Burst phase : nominalvalue -135 Burst suppressioninternal
Figure 7 : PAL-M Typical VBI Waveforms, Non-interlaced Mode ("CCIR-like" Line Numbering)
Full VBI Partial VBI 0V A B
256
257
258
259
260
261
262
1
2
3
4
5
6
7
8
9
10
16
17
Burst phase toggles every line
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0119A-14.EPS
0119A-13.EPS
STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) Figure 8 : Horizontal Blanking Interval and Active Video Timings
d
0H
b a c1 (bit "aline" = 0) c2 (bit "aline" = 1) NTSC-M a PAL-BDGHI
Full Digital Line Encoding (720 Pixels - 1440T) "Analog" Line Encoding (710 Pixels - 1420T)
PAL-N
PAL-M
5.38s (even lines) 5.52s (odd lines)
5.54s (A-type) 5.66s (B-type)
5.54s (A-type) 5.66s (B-type)
5.73s (A-type) 5.87s (B-type)
These are typical values. Actual values will depend on the static offset programmed for subcarrier generation.
b c1 c2 d
1.56s 8.8s 9.3s 9 Cycles of 3.58MHz
1.28s 9.3s 10.1s 10 Cycles of 4.43MHz
1.28s 9.3s 10.1s 9 Cycles of 3.58MHz
1.28s 9.3s
0119A-15.EPS
10.1s 9 Cycles of 3.58MHz
IV.3 - Reset Procedure Ahardware reset is performedby groundingthe Pin RESET. The master clock must be running and Pin RESET kept low for a minimum of 5 clock cycles. This sets the STV0119A in HSYNC+ODDEVEN (line-locked) slave mode, for NTSC-M, interlaced ITU-R601 encoding with MacrovisionTM copy protection revision 7.01 operating. Closed-captioning and Teletext encoding are all disabled. Then the configuration can be customized by writing into the appropriate registers. A few registers are never reset, their contents is unknown until the first loading (refer to the Register Contents and Description). It is also possible to perform a software reset by setting bit'softreset' in Reg 6. The IC's response in that case is similar to its response after a hardware reset, except that Configuration Registers (Reg 0 to 6) and a few other registers (see description of bit `softreset') are not altered .
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STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) IV.4 - Master Mode In this mode, the STV0119A supplies HSYNC and ODDEVEN sync signals (with independently programmable polarities) to drive other blocks. Refer to Figure 9 and 10 for timings and waveforms. The STV0119Astarts encoding and counting clock cycles as soon as the master mode has been loaded into the control register (Reg.0). Configuration bits "Syncout_ad[1:0]" (Reg4) allow to shift the relative position of the sync signals by up to 3 clock cycles to cope with any YCrCb phasing.
Figure 9 : ODDEVEN, VSYNC and HSYNC Waveforms
Active edge (programmable polarity) ODDEVEN (see Note 1) Active edge (programmable polarity) VSYNC Active edge (programmable polarity) HSYNC (see Note 2) 4 1 5 2 6 3 266 313 267 314 268 315 269 316
0119A-16.EPS
Line Numbers : SMPTE-525 CCIR-625
128 Tckref = 4.74s
Notes : 1. When ODDEVEN is a sync input, only one edge ("the active edge") of the incoming ODDEVEN is taken into account for synchronization. The "non-active" edge (2nd edge on this drawing) is not critical and its position may differ by H/2 from the location shown. 2. The HSYNC pulse width indicated is valid when the STV0119A supplies HSYNC. In those slave modes wher e it receives HSYNC, only the edge defined as active is relevant, and the width of the HSYNC pulse it receives is not critical.
Figure 10 : Master Mode Sync Signals
CKREF ODDEVEN (out)
Active Edge (programmable polarity)
1TCKREF
HSYNC (out)
Active Edge (programmable polarity)
YCRCB
Cr
Y'
Cb
Y
Cr
Y'
Note : 1. This figure is valid for bits "syncout_ad[1:0]" = default.
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0119A-17.EPS
Duration of HSYNC Pulse : 128 TCKREF
STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) IV.5 - Slave Modes Six slave modesareavailable : ODDEVEN+HSYNC based (line-based sync), VSYNC+HSYNC based (another type of line-based sync), ODDEVEN-only based(frame-based sync), VSYNC-onlybased(another type of frame-based sync), or sync-in-data based (line locked or frame locked). ODDEVEN refers to an odd/even (also known as not-top/bottom) field flag, HSYNC is a line sync signal, VSYNCis a vertical sync signal. Their waveforms are depicted in Figure 9. The polarities of HSYNC and VSYNC/ ODDEVEN a re independently programmable in all slave modes. IV.5.1- Synchronization onto a Line Sync Signal IV.5.1.1 - HSYNC+ODDEVEN Based Synchronization Synchronization is performed on a line-by-line basis by locking onto incoming ODDEVEN and HSYNC signals. Refer to Figure 11 for waveforms and timings. The polarities of the active edges of HSYNC and ODDEVEN are programmable and independent. The first active edge of ODDEVEN initializes the internal line counter but encoding of the first line does not start until an HSYNC active edge is detected (at the earliest, HSYNC may transition at the sametime as ODDEENV).At that point,the internal sample counter is initialized and encoding of the first line starts. Then, encoding of each subsequent line is individually triggered by HSYNC active edges. The phase relationship between HSYNC and the incoming YCrCB data is normally such that the first clock rising edge following the HSYNC active edge samples "Cb" (i.e. a `blue' chroma sample within the YCrCb stream). It is however possible to internally delay the incoming sync signals (HSYNC+ODDEVEN) by up to 3 clock cycles to cope with different data/sync phasings, using configuration bits "Syncin_ad" (Reg. 4). The STV0119A is thus fully slaved to the HSYNC signal, which means that lines may contain more or less samples than typical 525/625 system requirement. If the digital line is shorter than its nominal value: the sample counter is re-initialized when the `early' HSYNC arrives and all internal synchronization signals are re-initialized. If the digital line is longer than its nominal value : the sample counter is stopped when it reaches its nominal end-of-line value and waits for the `late' HSYNC before reinitializing. Thefield counteris incrementedon eachODDEVEN transition. The line counter is reset on the HSYNC following each active edge of ODDEVEN. IV.5.1.2- HSYNC+VSYNC Based Synchronization Synchronization is performed on a line-by-line basis by locking onto incoming VSYNC and HSYNC signals. Refer to Figure 12 for waveforms and timings. The polarities of HSYNC and VSYNC are programmable and independent. The incoming VSYNC signal is immediately transformed into a waveform identical to the odd/even waveform of an ODDEVEN signal, therefore the behavior of the core is identical to that described above for ODDEVEN+HSYNC based synchronization. Again, the phase relationship between HSYNC and the incoming YCrCb data is normally such that the first clock rising edge following the HSYNC active edge samples "Cb" (i.e. a `blue' chroma sample within the YCrCb stream). It is however possible to internally delay the incoming sync signals (HSYNC+VSYNC) by up to 3 clock cycles to cope with different data/sync phasings, using configuration bits "Syncin_ad" (Reg. 4). The field counter is incremented on each active edge of VSYNC.
Figure 11 : HSYNC + ODDEVEN Based Slave Mode Sync Signals
CKREF
Active Edge (programmable polarity)
ODDEVEN (in)
Active Edge (programmable polarity)
HSYNC (in) YCRCB
Cb
Y
Cr
Y'
Cb
Note : 1. This figure is valid for bits "syncin_ad[1:0]" = default.
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0119A-18.EPS
STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) Figure 12 : HSYNC + VSYNC Based Slave Mode Sync Signals
CKREF Active Edge (programmable polarity) VSYNC (in) Active Edge (programmable polarity) HSYNC (in) YCRCB Cb Y Cr Y' Cb
Notes : 1. This figure is valid for bits "syncin_ad[1:0]" = default. 2. The active edges of HSYNC and VSYNC should normally be simultaneous. It is permissible that HSYNC transitions before VSYNC, but VSYNC must not transition before HSYNC.
Figure 13 : ODDEVEN Based Slave Mode Sync Signals
CKREF
Active Edge (programmable polarity)
ODDEVEN (in) YCRCB
Cb
Y
Cr
Y'
Cb
Note : 1. This figure is valid for bits "syncin_ad[1:0]" = default.
IV.5.2- Synchronization onto a Frame Sync Signal IV.5.2.1- ODDEVEN-only Based Synchronization Synchronizationis performed on a frame-by-frame basis by locking onto an incoming ODDEVEN signal. A line sync signal is derived internally and is also output as HSYNC. Refer to Figure 13 for waveforms and timings. The phase relationship between ODDEVEN and the incomingYCrCB data is normally such that the first clock rising edge following the ODDEVEN active edge samples "Cb" (i.e. a `blue' chroma sample within the YCrCb stream). It is however possible to internally delay the incoming ODDEVEN signal by up to 3 clock cycles to cope with different data/sync phasings, using configuration bits "Syncin_ad" (Reg. 4). The first active edge of ODDEVEN triggersgeneration of the analog sync signals and encoding of the incomingvideo data. Frames being supposedto be of constant duration, the next ODDEVEN active transitionis expected at a precise time after the last ODDEVEN detected. So, once an active ODDEVEN edge has been detected, checks that the following ODDEVEN are present at the expected instants are performed. Encoding and analog sync generation carry on un-
less three successive fails of these checks occur. In that case, three behaviors are possible, according to the configuration programmed (Reg. 1-2) : - if `free-run' is enabled, the STV0119A carries on outputtingthe digital line sync HSYNC and generating analog video just as though the expected ODDEVEN edge had been present. However, it will re-synchronizeontothe next ODDEVENactive edge detected, whatever its location. - if `free-run' is disabled but bit `sync_ok' is set in configuration register1, the STV0119A sets the active portion of the TV line to black level but carries on outputting the analog sync tips (on Ys and CVBS) and the digital line sync signal HSYNC. (When programmed, MacrovisionTM pseudo-sync pulses and AGC pulses are also present in the analog sync waveform). - if `free-run' is disabled and the bit `sync_ok' is not set, all analog video is at black level and neither analog sync tips nor digital line sync are output. Note that this mode is a frame-based sync mode, as opposedtoa field-basedsync mode, that is, only one type of edge (rising or falling, according to bit `polv'in Reg 0) is of interest to the STV0119A, the other one is ignored.
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0119A-20.EPS
0119A-19.EPS
STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) IV.5.2.2 - VSYNC only Based Synchronization Synchronization is performed on a frame-by-frame basis by locking onto an incoming VSYNC signal. An auxiliary line sync signal HSYNC must also be fed to the STV0119A, which uses it to reconstruct from VSYNC and HSYNC information an internal odd/even waveform identical to that of an ODDEVEN signal. Therefore the behavior of the core is identicalto that describedabove for ODDEVENonly basedsynchronization(exceptthat nothingis output on HSYNC pin since it is an input port in that mode). Note that HSYNC is an input but has no other use than allowing the STV0119Ato decide whether an incoming VSYNC pulse flags an odd or an even field. In other words, the STV0119A does not lock onto HSYNC in this mode since this is NOT a line-locked mode. The phase relationship between VSYNC and the incoming YCrCb data is normally such that the first clock rising edge following the VSYNC active edge samples "Cb" (i.e. a `blue' chroma sample within the YCrCb stream). It is however possible to interna lly d e la y t h e in c o ming s y n c s ig na ls (VSYNC+HSYNC) by up to 3 clock cycles to cope with different data/sync phasings, using configuration bits "Syncin_ad" (Reg. 4). IV.5.3 - Synchronization onto Data-embedded Sync Words IV.5.3.1 - `End-of-frame' Word Based Synchronization Synchronization is performed by extracting the 1to-0 transitions of the `F' flag (end-of-frame) from the `EAV' (End-of-Active Video) sequence embedded within ITU-R656 / D1 compliant digital video streams. Both a frame sync signal and a line sync signal are derived and are made available externally as ODDEVEN and HSYNC (see Figure 14). The first successful detection of the `F' flag triggers generationof theanalog sync signals and encoding of the incoming video data. Frames being supposed to be of constant duration, the next EAV word containingthe `F' flag is expected at a precise time after the latest detection. So, once an active `F' flag has been detected, checks that the following flags are present within the incoming video stream at the expected times are performed. Encoding and analog sync generation carry on unless three successive fails of these checks occur. In that case, three behaviors are possible, according to the configuration programmed : - if `free-run' is enabled, the STV0119A carries on generating the digital frame and line syncs (ODDEVEN and HSYNC) and generating analog video just as though the expected `F' flag had been present. However, it will re-synchronize onto the next `F' flag detected within the incoming CCIR656/D1 video stream. - if `free-run' is disabled but the bit `sync_ok' is set in the configuration registers, the STV0119A sets the active portion of the TV line to black level but carries onoutputtingthe analogsynctips (on Ys andCVBS) andthedigitalframeandlinesyncsignalsODDEVEN and HSYNC. (When programmed, MacrovisionTM pseudo-sync pulses and AGC pulses are also present in the analog sync waveform). - if `free-run'is disabledandthe bit `sync_ok'is notset, all analog video is at black level and neither analog sync tips nor digital frame/line sync are output. The SAV and EAV words are Hamming-decoded. After detection of two successive errors, a bit is set in the status register to inform the micro-controller of the poor transmission quality. IV.5.3.2 - `End-of-line' Word Based Synchronization Synchronization is performed by extracting the `F' and `H' flags from the `SAV' (Start of Active Video) and `EAV' (End of Active Video) words embedded within ITU-R656/D1 compliantdigitalvideo streams. Aline sync signaland a framesync signalare derived internally from these flags and are output on the HSYNC and ODDEVEN/VSYNC pins in output mode. These signals are also exploited by the core of the circuit which treats them like it treats incoming ODDEVEN and HSYNC signals in HSYNC+ODDEVEN based synchronization (see Section IV.5.1.1).
Figure 14 : Data (EAV) Based Slave Mode Sync Signals
CKREF YCRCB
FF
00 EAV
00
B6
Cb
Y 46TCKREF 1TCKREF HSYNC Duration : 128TCKREF
HSYNC (out)
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0119A-21.EPS
ODDEVEN (out)
STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) IV.6 - Input Demultiplexer The incoming 27Mbit/s YCrCb data is demultiplexed into a `blue-difference' chroma information stream, a `red-difference' chroma information stream and a luma information stream. Incoming data bits are treated as blue, red or luma samples according to their relative position with respect to the sync signals in use and to the content of configuration bits "Syncin_ad" (slave modes) or "Syncout_ad" (master mode). The ITU-R601 recommendation defines the black luma level as Y = 16dec and the maximum white luma level as Y = 235dec. Similarly it defines 225 quantization levels for the color difference components (Cr, Cb), centered around 128. Accordingly, incoming YCrCB samples can be saturated in the input multiplexer with the following rules : - for Cr or Cb samples : Cr, Cb > 240 Cr, Cb saturated at 240 Cr,Cb < 16 Cr, Cb saturated at 16 - for Y samples : Y > 235 Y saturated at 235 Y < 16 Y saturated at 16 This avoids having to heavily saturate the composite video codes before digital-to-analog conversion in case erroneous or unrealistic YCrCb samples are input to the encoder (there may otherwise be overflow errors in the codes driving the DACs), and therefore avoids genera-ting a distorded output waveform. However, in some applications, it may be desirable to let `extreme' YCrCb codes pass through the demultiplexer. This is also possible, provided that bit "maxdyn" is set in configuation register 6. In this case, only codes 00hex and FFhex are overridden: if such codes are found in the active video samples, they are forced to 01hex and FEhex. In any case, the YCrCb codes are not overridden for EAV/SAV decoding The demultiplexer is also able to handle 54Mbit/s YCrCb streams for dual encodingapplications. Refer to Section IV.17, "Dual Encoding Application 54Mbit/s YCrCB interface". IV.7 - Sub-carrier Generation A Direct Digital Frequency Synthesizer (DDFS) using a 24-bit phase accumulator, generates the required color sub-carrier frequency.This oscillator feeds a quadraturemodulator which modulatesthe baseband chrominance components. The sub-carrier frequency is obtained from the following equation : 24 Fsc = (24-bit Increment Word / 2 ) x CKREF Hard-wired Increment Word values are available for each standard(except for `NTSC-4.43') and can be automatically selected. Alternatively (according to bit `selrst' in Reg. 2.), the frequency can be fully customized by programming other values into a dedicated Increment Word Register (Reg. 10-1112). This allows for instance to encode "NTSC4.43" or "PAL-M-4.43". This is done with the following procedure : - Program the required increment in Registers 10 to 12 - Set bit `selrst' to `1' in Configuration Register 2 - Perform a software reset (Reg. 6). Caution : this sets back all bits from Reg. 7 onwards to their default value, when they can be reset. Warning : if a standard change occurs after the software reset, the increment value is automatically re-initialized with the hardwired or loaded value according to bit selrst. The reset phase of the color sub-carrier can also be software-controlled (Reg. 13-14). The sub-carrier phase can be periodically reset to its nominal value to compensate for any drift introduced by the finite accuracy of the calculations. Sub-carrier phase adjustment can be performed every line, every eight field, every four field, or every two field (Register 2 bits valrst[1:0]).
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STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) IV.8 - Burst Insertion The color reference burst is inserted so as to always start with a positive zero crossing of the subcarrier sine wave (except in some cases where MacrovisionTM anti-copyprocess is active). Thefirst and last half-cycles have a reduced amplitude so that the burst envelope starts and ends smoothly. The burst contains 9 or 10 sine cycles of 4.43361875MHzor 3.579545MHzaccordingto the standard programmed in the Control Register (Reg. 0, bits std[1:0]), as follows : - NTSC-M 9 cycles of 3.579542MHz - PAL-BDGHI 10 cycles of 4.43361875MHz - PAL-M 9 cycles of 3.57561149MHz - PAL-N 9 cycles of 3.5820558MHz It is possibleto turn the burst off (no burst insertion) by setting configurationbit `bursten'to 0 (register2).
Notes : - Two strategies exist for burst insertion: one is to merely gate and shape the subcarrier for burst insertion, the other is more elaborated and is to always start the burst with a positive-going zero crossing. In the first case the phase of the subcarrier when the burst starts is not controlled, with the consequence that some of its first and last cycles are more heavily dis torded. The second solution guarantees smooth start and endof burst witha maximum of undistorded burst cycles and can only be beneficial to chroma decoders, it is the solution implemented in the STV0119A. - While the first option gave constant burst start time but uncontrolled initial burst phase, the second solution guarantees start on a positive-going zero crossing with the consequence that two burst start locations are visible over successive lines, according to the line parity. This is normal and explained below. - In NTSC, the relation between subcarrier frequency and line length creates a 180o subcarrier phase difference (with respect to the horizontal sync) from one line to the next according to the line parity. So if the burst always starts with the same phase (positive-going zero crossing), this means the burst will be inserted at time X or at time X+TNTSC/2 after the horizontal sync tip according to the line parity, where TNTSC is the duration of one cycle of the NTSC burst. - With PAL, a similar rationale holds, and again there will be two possible burst start locations. The subcarrier phase difference (with respect to the horizontal sync) from one line to the next in that case is either 0 or 180o with the following series: A-A-B-B-A-A-...-etc. where A denotes `A-type' bursts and B denotes `B-type' bursts, A-type and B-type being 180 out of phase with respect to the horizontal sync. So 2 locations are possible, one for A-type, the other for B-type (see Figure 8). - This assumes a periodic reset of the subcarrier is automatically performed (see bits valrst[1:0] in Reg 2). Otherwise, over several frames, the start of burst will drift within an interval of one a subcarrier's cycle. THIS IS NORMAL and means the burst is correctly locked to the colors encoded. The equivalent effect with a gated burst approach would be the following : the start location would be fixed but the phase with which the burst starts (with respect to the horizontal sync) would be drifting.
chronization pulses. The interpolationfilter compensates for the sin(x)/ x attenuation inherent to D/A conversion and greatly simplifies the output stage filter (refer to Figures 15 to 17 for characteristic curves). Figure 15 : Luma Filtering Including DAC Attenuation
0 -5 Amplitude (dB) -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Frequency (x106) (Hz)
0119A-22.EPS 0119A-24.EPS 0119A-23.EPS
Figure 16 : Luma Filtering with 3.58MHz Trap, Including DAC Attenuation
0 -5 Amplitude (dB) -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Frequency (x106) (Hz)
Figure 17 : Luma Filtering with 4.43MHz Trap, Including DAC Attenuation
0 -5 Amplitude (dB) -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Frequency (x106) (Hz)
IV.9 - Luminance Encoding The demultiplexed Y samples are band-limitedand interpolated at CKREF clock rate. The resulting luminancesignal is properlyscaled before insertion of any Closed-captions, CGMS or Teletext data, MacrovisionTM copy-protection signals and syn16/42
STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) In addition, the luminance that is added to the chrominance to create the composite CVBS signal can be trap-filtered at 3.58MHz (NTSC) or 4.43MHz (PAL). This allows to cope with application oriented towards low-end TV sets which are subject to cross-color if the digital source has a wide luminance bandwidth (e.g. some DVD sources). Note that the trap filter does not affect the S-VHS luminance output nor the RGB outputs. A 7.5 IRE pedestal can be programmed if needed with all standards (see Reg1, bit setup). This allows in particular to encode Argentinian and non-Argentinian PAL-N, or Japanese NTSC (NTSC with no set-up). A programmable delay can be inserted on the luminance path to compensate any chroma/luma delay introduced by off-chip filtering (chroma and luma transitionsbeing coincidentat the DAC output with default delay) (Reg3, bits del[2:0]). IV.10 - Chrominance Encoding U and V chroma components are computed from demultiplexed Cb, Cr samples. Before modulating the subcarrier, these are band-limited and interpolated at CKREF clock rate. This processing eases the filtering following D/A conversion and allows a more accurate encoding. A set of 4 different filters is available for chroma filtering to fit a wide variety of applications in the different standards and include filters recommendedby ITU-R Rec624-4 and SMPTE170-M. The available 3dB bandwidths are 1.1, 1.3, 1.6 or 1.9MHz, refer to Figures 18 to 22 for the various frequency responses (Reg1, bits flt[1:0]). The narrower bandwidths are useful against crossluminance artefacts, the wider bandwidths allow to keep higher chroma contents and then an improved image quality. IV.11 - Composite Video Signal Generation The composite video signal is created by adding the luminance (after optional trap filtering, Reg 3 bits entrap and trap_pal) and the chrominance components.A saturationfunctionis includedin the adder to avoid overflow errors should extreme luminance levels be modulated with highly saturated colors (this does not correspond to natural colors but may be generated by computers or graphic engines). A `color killing' function is available (Reg 1, bit coki) whereby the composite signal contains no chrominance, i.e. replicates the trap-filtered luminance. Note that this function does not suppress the chrominance on the S-VHS outputs (nevertheless suppressing the S-VHS chrominance is possible using bit "bkg_c" in Reg 5). Figure 18 : Various Chroma Filters Available + RGB Filter
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9
Amplitude (dB)
RGB f3=2.45 f3=1.9 f3=1.6 f3=1.3 f3=1.1
0119A-25.EPS 0119A-27EPS 0119A-26.EPS
0
0.5
1 1.5 2 2.5 Frequency (x106) (Hz)
3
3.5
Figure 19 : 1.1MHz Chroma Filter (flt = 00)
0 -5 -10 Amplitude (dB) -15 -20 -25 -30 -35 -40 0 2 4 6 8 10 Frequency (x106) (Hz) 12 14
Figure 20 : 1.3MHz Chroma Filter (flt = 01)
0 -5 -10 Amplitude (dB) -15 -20 -25 -30 -35 -40 0 2 4 6 8 10 Frequency (x106) (Hz) 12 14
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STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) Figure 21 : 1.6MHz Chroma Filter (flt = 10)
0 -5 -10 Amplitude (dB) -15 -20 -25 -30 -35 -40 0 2 4 6 8 10 Frequency (x106) (Hz) 12 14
0119A-28.EPS 0119A-29.EPS
Figure 22 : 1.9MHz Chroma Filter (flt = 11)
0 -5 -10 Amplitude (dB) -15 -20 -25 -30 -35 -40 0 2 4 6 8 10 Frequency (x106) (Hz) 12 14
IV.12 - RGB Encoding After demultiplexing, the Cr and Cb samples feed a 4 times interpolation filter. The resulting baseband chroma signal has a 2.45MHz bandwidth (Figure 23) and is combined with the filtered luma component to generate R, G, B samples at 27MHz. Figure 23 : RGB Chroma Filtering
0 -5 -10 Amplitude (dB) -15
IV.13 - Closed Captioning Closed-captions (or data from an Extended Data Service as defined by the Closed-Captions specification) can be encoded by the circuit. The closed caption data is delivered to the circuit through the I2C interface. Two dedicated pairs of bytes (two bytes per field), each pair preceded by a clock run-in and a start bit can be encoded and inserted on the luminance path on a selected TV line. The Clock Run-In and Start code are generatedby the STV0119A. Closed-caption data registers are double-buffered so that loading can be performed anytime, even during line 21/284 or any other selected line. User register 39 (resp. 41) contains the first byte to send (LSBfirst) after the start bit on the appropriate TV line in field 1 (resp. field 2), and user register 40 (resp. 42) contains the second byte to send. The TV line number where data is to be encoded is programmble (Reg. 37, 38). Lines that may be selected include those used by the StarSight data broadcastsystem. Closed-captions data has priority over any CGMS or Macrovisionanticopy signals programmed for the same line. The internal Clock Run-In generator is based on a Direct Digital Frequency Synthesizer. The nominal instantaneousdata rate is 503.5kbit/s(i.e. 32 times the NTSC line rate). Data LOW corresponds nominally to 0 IRE, data HIGH corresponds to 50 IRE at the DAC outputs. Refer to Figure 24. When closed-captioning is on (bits cc1/cc2 in Reg.1), the CPU should load the relevant registers (reg. 39 and 40, or 41 and 42) once every frame at most (although there is in fact some margin due to the double-buffering).Two bits are set in the status register in case of attempts to load the closed-caption data registers too frequently, these can be used to regulate loading rate. Figure 24 : Example Closed-caption Waveform
300 250 200 LSB 150 100
13.9s 7 cycles of 504kHz 61s Transition Time : 220ns 10s 27.35s
-20 -25 -30
0119A-30.EPS
-40
0
2
4 6 8 10 Frequency (x106) (Hz)
12
14
0
t
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0119A-31.EPS
-35
50
STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) The closed caption encoder considers that closed caption data has been loaded and is valid on completion of the write operation into register 40 for field1, intoregister42 for field2. If closed caption encodinghas been enabled and no new data bytes have been written into the closed caption data registers when the closed caption window starts on the appropriateTV line, then the circuit outputstwo US-ASCII NULL characterswith odd parity after the start bit. IV.14 - CGMS Encoding CGMS (Copy Generation Management System also known as VBID and described by standard CPX-1204 of EIAJ) data can be encoded by the circuit. Three bytes (20 significant bits) are deliv2 ered to the chip via the I C interface.Two reference bits (`1' then `0') are encoded first, followed by 20 bits of CGMS data (including a Cyclic Redundancy Check sequence, not computed by the device and supplied to it as part of the 20 data bits). The reference bits are generated locally by the STV0119A. Refer to Figure 25 for a typical CGMS waveform. When CGMS encoding is enabled, the CGMS (see bit encgms in Reg 3) waveform is continously present once in each field, on lines 20 and 283 (SMPTE-525 line numbering). CGMS data has priority over any Macrovision anticopy signals programmed for the same line. The CGMS data register is double-buffered,which means that it can be loaded anytime (even during line 20/283) without any risk of corrupting CGMS data that could be in the process of being encoded.The CGMS encoder considers that new CGMS data has been loaded and is valid on completion of the write operation into register 33 Figure 25 : Example CGMS Waveform
300 250 200 LSB
11s
IV.15 - Teletext Encoding The STV0119A is able to encode Teletext according to the "CCIR/ITU-R Broadcast Teletext System B" specification, also known as "World System Teletext". In DVB applications, Teletext data is embedded within DVB streams as MPEG data packets. It is the responsibilityof a "TransportLayer Processing" IC (or demultiplexer), like ST's ST20-based "TP2", to sort out incoming data packets and in particular to store Teletext packet in a buffer, which then passes them to the STV0119A on request. IV.15.1 - Signals Exchanged The STV0119Aand the Teletext buffer exchange 2 signals: TTXS (Teletext Synchronization) going from the STV0119Ato the Teletext Bufferand TTXD (Teletext Data) going from the Teletext Buffer to the STV0119A. The TTXS signal is a request signal generated on selected lines. In response to this signal, the Teletext buffer is expected to send 360 Teletext bits to the STV0119Afor insertion of a Teletext line into the analog video signal. The durationof the TTXS windowis 1402reference clockperiods (51.926s), which correspondsto the duration of 360 Teletext bits (see Transmission Protocol below). Following the TTXS rising edge the encoder expects data from the Teletext buffer after a programmable number (2 to 9) of 27MHz master clock periods. Data is transmittedsynchronouslywith the master clock at an average rate of 6.9375Mbit/s according to the protocol described below. It consists, in order of transmission, of 16 Clock Run-In bits, 8 Framing Code bits and the 336 bits (42 bytes) that represent one Teletext packet. IV.15.2 - Transmission Protocol In order to transmit the Teletext data bits at an average rate of 6.9375Mbit/s, which is about 1/3.89 times the master clock frequency, the following scheme is adopted : The 360-bit packet is regarded as nine 37-bit sequences plus one 27-bit sequence. In every sequence, each Teletext data bit is transmitted as a succession of 4 identicalsamples at 27 Msample/s, except for the 10th, 19th, 28th and 37th bits of the sequence which are transmitted as a succession of 3 identical samples. This protocol is compatible with ST's ST-20 based Tranport Layer IC ("TP2").
150 100 50
Bit 1 Word 0 6 bits
48.7s
Word 1 Word 2 4 bits 4 bits CRCC 6 bits Bit 20
0
t
0119A-32.EPS
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STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) Figure 26 : "TTXS Rising" to "First Valid Sample" Delay for txdl[2:0] = 0
CKREF
TTXS
TTXD
Not Valid
Bit 1
Bit 2
IV.15.3 - Programming IV.15.3.1 - 'TTXS Rising' to 'First Valid Sample' Delay Programming Theencoder expects the Teletextbuffer to clock out the first Teletext data sample on the (2+N)th rising edge of the master clock following the rising edge of TTXS (Figure 26 depicts this graphically for N=0). 'N' is programmable from 0 to 7 (i.e. overall delay is programmable from TWO to NINE 27MHz cycles) via 3 dedicated bits located in the Configuration Register4 : "txdl[2:0]". IV.15.3.2 - Teletext Line Selection Five dedicated registers allow to program Teletext encoding in various areas of the Vertical Blanking Interval (VBI) of each field. A total of 4 such areas (i.e. blocks of contiguous Teletext lines) can independently be defined within the two VBIs of one frame (e.g. 2 blocksin each VBI, or 3 blocks in field1 VBI and one in field2 VBI, etc.). Further, under certain circumstances, it is possible to define up to 4 areas in each VBI. Programming is performed using 4 "Teletext Block De f in itio n" re g is t ers (T TX BD1 , T TXB D2, TTXBD3,TTXBD4) and a "Teletext Block Mapping" register (TTXBM). Refer to the description of user registers 34 to 38 for details. IV.15.4 - Teletext Pulse Shape The shape and amplitude of a singleTeletext pulse are depictedin Figure27, its relativepower spectral density is given in Figures 28 and 29 and is substantially zero at frequencies above 5MHz, as re-
quired by the World System Teletext specification. Figure 27 : Shape and Amplitude of a Single Teletext Symbol
70 60 50 40 IRE 30 20 10 0 -150 -144ns -100 -50 0 (ns) 50 100 150 +144ns
0119A-34.EPS 0119A-35.EPS
Figure 28 : Linear PSD Scale
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
PSD (dB)
0
1
2
3 4 5 (x106) (Hz)
6
7
8
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0119A-33.EPS
(txdl[2:0] + 2) TCKREF
STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) Figure 29 : Logarithmic PSD Scale
0 -10 -20 PSD (dB) -30 -40 -50 -60
0119A-36.EPS A5
After a hardware reset, it is these addresses that the STV0119A recognizes.
2 It is possible to modify the default I C address by tiing the TTXS/CSI2C pin to logic `1' and validating the change by writing into a dedicated bit in Register 6.
In that case, the STV0119Ahas a newI 2C address : - in write mode : "01000010" (42 hex) - in read mode : "01000011"(43 hex) Once the I 2C address has been changed, it cannot be modifed anymore until the next hardware reset. Note that these I2C addresses are the same as those used by the STV0117/STV0117A (others ST PAL/NTSC Digital Encoder). It is expected that I2C address changes will normally be needed for dual encoding applications. The exact procedure to change the I2C addresses is detailed below, in the section that deals with dual encoding applications. Write and read operations are described in Figures 30 and 31.
-70 -80 0 1 2 3 4 5 (x106) (Hz) 6 7 8
IV.16 - I2C Bus An external micro-controller controls the STV0119A via an I2C busby writing into or readingfrom internal registers. The I2C interface supports the "fast I2C protocol" (up to 400kHz - and potentially more). The default I2C addresses of the STV0119A are : - in write mode : "01000000" (40 hex) - in read mode : "01000001" (41 hex)
Figure 30 : I2C Write Operation (default address at power-on, CSI2C '1')
SCL
SDA Start I2C Slave Address 40h
R/W ACK by STV0119
A7
A6
A4
A3
A2
A1
A0 ACK by STV0119
D7
D6
D5
D4
D3
D2
D1
D0 ACK by STV0119
LSB Address
Data Byte 1
SCL
Data Byte 2
ACK by STV0119
Data Byte 3
ACK by STV0119
Data Byte n
ACK by STV0119
Stop
Figure 31 : I2C Read Operation (default address at power-on, CSI2C '1')
SCL
SDA
Start
2
R/W
A7 ACK by STV0119
A6
A5
A4
A3
A2
A1
A0
I C SlaveAddress 40h
LSB Address
ACK by STV0119
Stop
SCL
R/W
0119A-38.EPS
SDA
Start
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
I2C SlaveAddress 41h
ACK by STV0119
Data Byte 1
ACK by micro
Data Byte n
ACK by micro
Stop
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0119A-37.EPS
SDA
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) IV.17 - Dual Encoding Application with 54Mbit/s YCrCb Interface The STV0119A is able to interface with ST's MPEG decoders capable of supplying a 54-Mbit/s YCrCBmultiplex, like the STi3520M. This multiplex embeds two 27Mbit/s YCrCb video streams, one with OSD contents and the other without OSD content (see Figure 32). Note that the frequency of the reference clock supplied to the encoder is still 27MHz, only both edges are used in the interface. The MPEG decoder being usually slaved to the encoder, if two encoders are to be used in parallel, one of them must be master and the other must be slave. Figure 33 shows a typical dual encoding application (although other applications where two STV0119A's are slave are possible). It is also necessary to be able to control independently the encoders. One solution is to have two separate I2C busses (one for each encoder) running from the microcontroller(this is possible on ST's ST20, which features two I2C busses), another solution is to change the I2C chip address of one of the STV0119A. This can be done with the following procedure : - If no Teletext is required, tie pin TTXS/ CSI2C of Figure 32 : 54Mbit/s Dual YCRCB Stream
CKREF (27MHz) 54Mbit/s YCRCB Stream
0119A-39.EPS
the 1st encoder to `0'. - If Teletext encoding is needed, connect the TTXS/CSI2C pin of the first encoder to both the TTXS input pin of the Teletext Buffer / Transport IC (e.g. ST's TP2) and a pull-down resistor (needed for power-on configuration). - Connect TTXS/CSI2C of the second encoder to logic `1'. - Before performing any Teletext-related programming, set to `1' bit "chgi2c" in configuration register 6. On hardware reset, both encoders have the same default I2C address (40-41hex). When bit "chgi2c" toggles to `1', the I2C address of the first encoder (withTTXS/CSI2C pulled low) keeps unchanged at 40-41hex, whilst the I2C address of the second encoder (with TTXS/CSI2C = `1') switches to 4243hex and can no more be changed until the next hardware reset. After I2C address change, the second encoder must be programmedto choose the YCRCb incoming data stream on the falling edge of CKREF (see bit 'nosd' in configuration register 3).
Cbnosd
Cbosd
Ynosd
Yosd
Crnosd
Crosd
Y'nosd
Y'osd
Cbnosd Cbnosd
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STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) Figure 33 : Typical Dual Encoding Application
27MHz
STV0119A (Master)
VDD G/Y R/C B/CVBS CVBS SCL SDA 3.3V
3.3V
27MHz
3.3V
ODDEVEN HSYNC
With OSD For TV Set With OSD
VDD ODDEVEN HSYNC YCrCb[7:0]
MPEG Decoder (e.g. STi3520M)
8 Frame Sync Line Sync 8 54MHz Digital Video Data 3.3V
54MHz Interface Bit nosd = 0 TTXS/CSI2C
VSS
27MHz
3.3V Rpull-up Without OSD
0119A-40.EPS
VSS
Transport IC V DD TTXS (ST20TP2) (Demultiplexer + CPU + Teletext SDA Buffer) VSS SCL
3.3V
STV0119A (Slave)
VSS
TTXS/CSI2C (See Bit chgi2c)
ODDEVEN HSYNC 8 54MHz Interface Bit nosd = 1
SCL SDA G/Y R/C B/CVBS For VCR Without OSD
27MHz
CVBS
Rpull-up
Rpull-down = 47k
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STV0119A
IV - FUNCTIONAL DESCRIPTION (continued) IV.18 - Line Skip / Line Insert Capability This patented feature of the STV0119A offers the possibility to cut the cost of the application by suppressing the need for a VCXO. Ideally, the master clock used on the application board and fed to the MPEG decoding IC would have exactly same frequency as the clock that was used when the MPEG data was encoded. Obviously this is not realistic; up to now a solution commonlychosen is to dynamicallyadjust theclock on the board as closeto the `ideal' clock as possible with the help of time stamps embedded within the MPEG stream. Such a kind of tracking often involves the use of a VCXO : when the MPEG data bufferfills up to more than some thresholdthe clock frequency is increased, when it empties down to some other threshold the clock frequency is lowered. The STV0119A offers an alternative, cost-saving solution: by programming the two bits jump and dec_ninc in configuration Reg6, the STV0119A is able to reduce or increase the length of some frames in a way that will not introduce visible artefacts (even if comb-filtering is used). These bits should be set according to the level of the MPEG data buffer. Refer to Section VI.2 Register 6, Register 9 and Registers 21-22-23 for complete bit description. Operation with the STV0119Aas sync master is as follows : - If the MPEG data buffers fills up too much: set bit "jump" to `1' and bit "dec_ninc" to `1'.The STV0119A will reduce the length of the current frame (Bit "jump" will then automatically be reset to `0'). - If the MPEG data buffers empties too much: set bit "jump" to `1' and bit "dec_ninc" to `0'.The STV0119Awill increase the length of the current frame (Bit "jump" will then automatically be reset to `0'). These operations can be repeated until the MPEG data buffer is inside its fixed limits. It is also possible to use the line skip/repeat capability in non-interlaced mode. This functionalityof the STV0119Ais also available in slave mode, in this case the sync signals supplied to the STV0119Amust be in accordancewith the modified frame lengthes programmed. IV.19 - MacrovisionTM Copy Protection Process rev7.01/6.1 The chrominance, luminance and compositevideo signals and R,G,B video signals can be altered according to the MACROVISIONTM Copy Protection Process, Revision 7.01 and Revision 6.1. This process is controlled via the I2C bus. A programming document is available to those customers who have executed a license or a non-disclosure agreement with Macrovision Corporation. For all relevant information or document, please contact : MACROVISION Corporation : 1341 ORLEANS DRIVE SUNNIVALE, CALIFORNIA 94089 USA Fax : 1.408.743.8610 IV.20 - CVBS, S-VHS and RGB Analog Outputs Four out of six video signals (composite CVBS, S-VHS (Y/C) and RGB) can be directed to 4 analog output pins through 9-bit D/A converters operating at the reference clock frequency. The available combinations (see bit `rgb_nyc' in Reg5) are : S-VHS (Y/C) + CVBS + CVBS1 or : R, G, B + CVBS1. A single external analog power supply pair is used for all DACs, but two independent pairs of current and voltage references are needed. Each current reference pin is normally connected externally to a resistor tied to the analogue ground, whilst each voltage reference pin is normally connected to a capacitance tied to the analogue ground. The internal current sources are independentfrom the positive supply, thanks to a bangap, and the consumption of the DACs is constant whatever the codes converted. Any unused DAC may be independentlydisabled by software, in which case its output is at `neutral' level (blanking for luma and composite outputs, no color for chroma output, black for RGB outputs). For applications where a single CVBS output is required, the RGB/CVBS+S-VHS Triple DAC should be disabled and Pins IREF(RGB), VR_RGB tied to analog power supply.
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STV0119A
V - CHARACTERISTICS V.1 - Absolute Maximum Ratings
Symbol VDDx VIN VOUT IREF Toper Tstg Ptot DC Supply Voltage Digital Input Voltage Digital Output Voltage Analog Input Reference Current Operating Temperature Storage Temperature Total Power Dissipation Parameter Value -0.3, 4.0 -0.3, VDD + 0.3 -0.3, VDD + 0.3 2 0, +70 -40, +150 500 Unit V V V mA
o o
C C
mW
V.2 - Thermal Data
Symbol R th(j-a) Parameter DC Junction-Ambient Thermal Resistance with sample soldered on a PCB Typ. Value 76 Unit C/W
V.3 - DC Electrical Characteristics Tamb = 25C/70C, VDDA = VDD = 3.3V, unless otherwise specified
Symbol SUPPLY VDDA VDD IDDA IDD Analog Positive Supply Voltage Digital Supply Voltage Analog Current Consumption Digital Current Consumption 3.0 3.0 20 20 3.3 3.3 35 3.6 3.6 50 50 V V mA mA Parameter Test Conditions Min. Typ. Max. Unit
RIREF =1.2k, RL = 200, C L = 50pF, CKREF = 27MHz, VDD = 3.6V autotest mode, static input signals Low level (any other pins) High level (any other pins)
DIGITAL INPUTS VIL VIH IL CIN Input Voltage Input Voltage SCL and SDA - (5V tolerant) Except SCL and SDA Input Leakage Current Input Pins (see note 2) Bi-directional Pins Input Capacitance Input Pins Bi-directional Pins Output Voltage Output Voltage Output Voltage Resistance for reference Current Source for 3 D/A Converters Output Voltage Dyn DAC to DAC VO max code (tri-DAC only) LF Integral Non-linearity LF Differential Non-linearity 0.8 2.0 2.0 VIL min or VIH max -10 -10 0.1 5 Low level, IO = 2mA High level (IOH = -4mA) Low level (IOL = 4mA) IREF = VREF/RIREF, VREF = 1.12V typ. RIREF = 1.2k, RL = 200 (Max. code - Min. Code) RIREF = 1.2k, RL = 200 RIREF = 1.2k, RL = 200 RIREF = 1.2k, RL = 200 0.95 2 0.6 1.2 1.10 3 1 0.5 0.4 80 10 4.5 VDD A A pF pF V V V k VPP % LSB LSB V V
SDA OUTPUT VL VOH VOL RIREF VO DIGITAL OUTPUT
D/A CONVERTER
ILE DLE
Notes : 1. This product withstands 1.4kV (The MIL883C Norm requires 2.0kV). This product withstands 150V (The EIAJ Norm requires 200V). 2. The high value for input Pins is due to internal pull-down resistance.
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STV0119A
V - CHARACTERISTICS (continued) V.4 - AC Electrical Characteristics Tamb = 25C/70C, VDDA = VDD = 3.3V, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. Unit DIGITAL INPUT (YCRCB[7:0], HSYNC, VSYNC/ODDEVEN, TTXD) tsu tho Input Data Set-up Time Input Data Hold Time CKREF rising edge, CKREF = 27MHz CKREF rising edge, CKREF = 27MHz 6 3 ns ns
ACTIVE PERIOD FOR NRESET tRSTL Input Low Time 200 ns
REFERENCE CLOCK : CKREF 1/tC_REF tD_REF tR_REF tF_REF
2
Clock Frequency Clock Duty Cycle Clock Rise Time Clock Fall Time 35*
27 65* 5 5
MHz % ns ns
I C CLOCK : SCL tC_SCL tD_SCL tL_SCL Clock Cycle Time Clock Duty Cycle LOW Level Cycle Rpull_up = 4.7k 250 Rpull_up = 4.7k 50 2 MHz % ns
DIGITAL OUTPUTS (HSYNC, ODDEVEN, TTXS) tp Propagation Delay Time CKREF rising edge, CKREF = 27MHz, CL = 50pF 10 ns
* In case of double encoding these values must be compatible with the ycrcb transmitter.
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STV0119A
VI - REGISTERS VI.1 - Register Mapping
configuration0 configuration1 configuration2 configuration3 configuration4 configuration5 configuration6 reserved reserved status increment_dfs increment_dfs increment_dfs phase_dfs phase_dfs reserved reserved chipid revid reserved reserved line_reg line_reg line_reg cgms_bit_1-4 cgms_bit_5-12 cgms_bit_13-20 ttx_block_1_def. ttx_block_2_def. ttx_block_3_def. ttx_block_4_def. ttx_block_map c.c.c.F1 c.c.c.F1 c.c.c.F2 c.c.c.F2 cclif1 cclif2 reserved ... reserved R/W R/W R/W R/W R/W R/W R/W xxx xxx R R/W R/W R/W R/W R/W xxx xxx R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W xxx ... xxx 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 ... 63 std1 blkli nintrl entrap syncin _ad1 rgb_nyc softreset xxx xxx hok d23 d15 d7 o21 xxx xxx 0 0 xxx xxx ltarg8 ltarg0 lref1 bit5 bit13 ttxbs1.3 ttxbs2.3 ttxbs3.3 ttxbs4.3 opc11 opc12 opc21 opc22 xxx xxx xxx ... xxx std0 flt1 enrst trap_pal syncin _ad0 bkcvbs1 jump xxx xxx atfr d22 d14 d6 o20 xxx xxx 1 0 xxx xxx ltarg7 lref8 lref0 bit6 bit14 ttxbs1.2 ttxbs2.2 ttxbs3.2 ttxbs4.2 c117 c127 c217 c227 xxx xxx xxx ... xxx sync2 flt0 bursten encgms syncout _ad1 reserved xxx xxx b2_free d21 d13 d5 o19 xxx xxx 1 0 xxx xxx ltarg6 lref7 bit7 bit15 ttxbs1.1 ttxbs2.1 ttxbs3.1 ttxbs4.1 c116 c126 c216 c226 xxx xxx xxx ... xxx sync1 sync_ok xxx nosd syncout _ad0 reserved xxx xxx b1_free d20 d12 d4 o18 xxx xxx 1 0 xxx xxx ltarg5 lref6 bit8 bit16 ttxbs1.0 ttxbs2.0 ttxbs3.0 ttxbs4.0 c115 c125 c215 c225 l1_4 l2_4 xxx ... xxx sync0 coki selrst del2 aline bk_ys xxx xxx xxx fieldct2 d19 d11 d3 o17 xxx xxx 0 0 xxx xxx ltarg4 lref5 bit1 bit9 bit17 ttxbe1.3 ttxbe2.3 ttxbe3.3 ttxbe4.3 c114 c124 c214 c224 l1_3 l2_3 xxx ... xxx polh setup rstosc del1 txdl2 bk_c xxx xxx xxx fieldct1 d18 d10 d2 o16 xxx xxx 1 0 xxx xxx ltarg3 lref4 bit2 bit10 bit18 ttxbe1.2 ttxbe2.2 ttxbe3.2 ttxbe4.2 c113 c123 c213 c223 l1_2 l2_2 xxx ... xxx polv cc2 valrst1 del0 txdl1 bk_cvbs chgi2c xxx xxx fieldct0 d17 d9 d1 o23 o15 xxx S 1 1 xxx xxx ltarg2 lref3 bit3 bit11 bit19 ttxbe1.1 ttxbe2.1 ttxbe3.1 ttxbe4.1 c112 c122 c212 c222 l1_1 l2_1 xxx ... xxx freerun cc1 valrst0 xxx txdl0 dacinv maxdyn xxx xxx jumping d16 d8 d0 o22 o14 xxx xxx 1 1 xxx xxx ltarg1 lref2 bit4 bit12 bit20 ttxbe1.0 ttxbe2.0 ttxbe3.0 ttxbe4.0 c111 c121 c211 c221 l1_0 l2_0 xxx ... xxx
dec_ninc free_jump
ttxbmf1.1 ttxbmf1.2 ttxbmf1.3 ttxbmf1.4 ttxbmf2.1 ttxbmf2.2 ttxbmf2.3 ttxbmf2.4
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_0 - Configuration0
MSB Content Default std1 1 std0 0 sync2 0 sync1 1 sync0 0 polh 0 polv 1 LSB freerun 0
std[1:0] std1 0 0 (*) 1 1
std0 0 1 0 1
Standard Selected PAL BDGHI PAL N (see bit set-up) NTSC M PAL M
Note 1 : Standard on hardware reset is NTSC; any standard modification selects automatically the right parameters for correct subcarrier generation.
sync[2:0] sync2 sync1 sync0 Configuration (refer to Functional Description, Sections IV.4 and IV.5) 0 0 0 ODDEVEN based SLAVE mode (frame locked) 0 0 1 F only based SLAVE mode (frame locked) (*) 0 1 0 ODDEVEN+HSYNC based SLAVE mode (line locked) 0 1 1 `F'+'H' based SLAVE mode (line locked) 1 0 0 VSYNC-only based SLAVE mode (frame locked) (see Note) 1 0 1 VSYNC+HSYNC based SLAVE mode (line locked) 1 1 0 MASTER mode 1 1 1 AUTOTEST mode (color bar pattern)
Caution : In VSYNC-only based slave mode (sync[2:0]="100"), HSYNC is nevertheless needed as an input. Refer to Functional Description, Section IV.5.2.2.
polh (*) polv (*)
Synchro : active edge of HSYNC selection (when input) or polarity of HSYNC (when output) 0 HSYNC is a negative pulse (128 TCKREF wide) or falling edge is active 1 HSYNC is a positive pulse (128 TCKREF wide) or rising edge is active Synchro : active edge of ODDEVEN/VSYNC selection (when input) or polarity of ODDEVEN (when output) - See Note 2 0 Falling edge of ODDEVEN flags start of field1 (odd field) or VSYNC is active low 1 Rising edge of ODDEVEN flags start of field1 (odd field) or VSYNC is active high
Note 2 : In master mode : polarity of ODDEVEN output. In slave by F (from EAV) : polv = 0 (cf D1 encoding) and ODDEVEN polarity is the image of F extracted from EAV words.
freerun (*)
Refer to Functional Description, Section IV.5 0 disabled 1 Enabled
Caution : This bit is taken into account in ODDEVEN-only, VSYNC-only or `F' based slave modes and is irrelevant to other synchronization modes.
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_1 - Configuration1
Content Default MSB blkli 0 flt1 1 flt0 0 sync_ok 0 coki 0 setup 1 cc2 0 LSB cc1 0
blkli (*)
Vertical BlankingIntervalselectionfor activevideo lines area (refer to FunctionalDescription, Section IV.2 and Figures 2 to 7). 0 (`partial blanking') Only following lines inside Vertical Interval are blanked NTSC-M : lines [1..9], [263(half)..272] (525-SMPTE) PAL-M : lines [523..6], [260(half)..269] (525-CCIR) other PAL : lines [623(half)..5], [311..318] (625-CCIR) This mode allows preservation of VBI data embedded within incoming YCrCb, e.g. Teletext (lines [7..22] and [320..335]), Wide Screen signalling (full line 23), Video Programing Service (line16), etc.). 1 (`full blanking') All lines inside VBI are blanked NTSC-M : lines [1..19], [263(half)..282] (525-SMPTE) PAL-M : lines [523..16], [260(half)..279] (525-CCIR) other PAL : lines [623(half)..22], [311..335] (625-CCIR)
Note : blkli must be set to '0' when closed captions and are to be encoded on following lines : - in 525/60 system: before line 20(SMPTE) or before line 283(SMPTE) - in 625/50 system: before line 23(CCIR) or before line 336(CCIR) For CGMS and Teletext encodings, blkli value is not taken into account.
U/V Chroma filter bandwidth selection (Refer to Functional Description, Section IV.10 and Figures 4 and 5) flt1 flt0 3dB Bandwidth Typical Application 0 0 f-3 = 1.1MHz Low definition NTSC filter 0 1 f-3 = 1.3MHz Low definition PAL filter (*) 1 0 f-3 = 1.6MHz High definition NTSC filter (ATSC compliant) & PAL M/N (ITU-R 624.4 compliant) 1 1 f-3 = 1.9MHz High definition PAL filter: Rec 624 - 4 for PALBDG/I compliant sync_ok Availability of sync signals (analog and digital) in case of input synchronization loss with no free-run active (i.e. freerun=0) (Refer to Functional Description, Section IV.5) (*) 0 No synchro output signals 1 Output synchros available on YS, CVBS and, when applicable, HSYNC (if output port), ODDEVEN (if output port), i.e same behavior as free-run except that video outputs are blanked in the active portion of the line
Caution : This bit is taken into account in ODDEVEN-only, VSYNC-only or `F' based slave modes and is irrelevant to other synchronization modes.
flt[1:0]
Color killer (Refer to Functional Description, Section IV.11) 0 Color ON 1 Color suppressed on CVBS (and CVBS1) outputsignal (CVBS=YS) but color still present on C andRGB outputs.For color suppressionon chromaDAC `C',see register 5 bitbkg_c. setup Pedestal enable (Refer to Functional Description, Section IV.9) 0 Blanking level and black level are identical on all lines (ex : Argentinian PAL-N, Japan NTSC-M, PAL-BDGHI) (*) 1 Black level is 7.5 IRE above blanking level on all lines outside VBI (ex :Paraguayan and Uruguayan PAL-N) In all standards, gain factor is adjusted to obtain the required levels for chrominance. cc2, cc1 Closed caption encoding mode (Refer to Functional Description, Section IV.13) cc2 cc1 Encoding Mode (*) 0 0 No closed caption/extendeddata encoding 0 1 Closed caption/extendeddata encoding enabled in field 1 (odd) 1 0 Closed caption/extendeddata encoding enabled in field 2 (even) 1 1 Closed caption/extendeddata encoding enabled in both fields (*)
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coki
STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_2 - Configuration2
MSB Content Default nintrl 0 enrst 0 bursten 1 xxxx 0 selrst 0 rstosc 0 valrst1 0 LSB valrst0 0
Refer to Functional Description, Section IV.7. nintrl (*) Non-interlaced mode select (Refer to Figures 3, 5 and 7) 0 Interlaced mode (625/50 or 525/60 system) 1 Non-interlaced mode(2x312/50 or 2x262/60 system)
Note : `nintrl' update is internally taken into account on beginning of next frame.
enrst (*) bursten (*) selrst (*)
Cyclic update of DDFS phase 0 No cyclic subcarrier phase reset 1 Cyclic subcarrier phase reset depending of valrst1 and valrst0 (see below) Chrominance burst control 0 Burst is turned off on CVBS (and CVBS1), C and RGB outputs are not affected 1 Burst is enabled Selects set of reset values for Direct Digital Frequency Synthesizer 0 Hardware reset values for phase and increment of subcarrier oscillator (see description of registers 10 to 14 for values) 1 I2C loaded reset values selected (see contents of Registers 10 to 14) Software phase reset of DDFS (Direct Digital Frequency Synthesizer) 0 inactive 1 a 0-to-1 transition resets the phase of the subcarrier to either the hard-wired default phase value or the value loaded in Register 13-14 (according to bit `selrst')
Note : Bit `rstosc' is automatically set back to `0' after the oscillator reset has been performed.
rstosc (*)
valrst[1:0] Note : valrst[1:0] is taken into account only if bit `enrst' is set valrst1 valrst0 Selection (*) 0 0 Automatic reset of the oscillator every line 0 1 Automatic reset of the oscillator every 2nd field 1 0 Automatic reset of the oscillator every 4th field 1 1 Automatic reset of the oscillator every 8th field Resetting the oscillator means here forcing the value of the accumulator phase to its nominal value to avoid accumulating errors due to the finite number of bits used internally. The value to which the accumulator is reset is either the hard-wired default phase value or the value loaded in Register 13-14 (according to bit `selrst'), to which a 0, 90, 180, or 270 correction is applied according to the field and line on which the reset is performed.
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_3 - Configuration3
MSB Content Default entrap 0 trap_pal 0 encgms 0 nosd 0 del2 0 del1 0 del0 0 LSB xxx 0
entrap (*)
Enable trap filter 0 Trap filter disabled 1 Trap filter enabled
trap_pal Refer to Functional Description, Section IV.9 Note : `trap_pal' is taken into account only if bit `entrap' is set. (*) 0 To select the NTSC trap filter (centered around 3.58MHz) (see Figure 16) 1 To select the PAL trap filter (centered around 4.43MHz) (see Figure 17) (*) encgms CGMS encoding enable (Refer to Functional Description, Section IV.14) 0 Disabled 1 Enabled
Note : When encgms is set to 1 Closed-Captions/Extended Data Services should not be programmed on lines 20 and 283 (525/60, SMPTE line number convention).
nosd (*)
Choice of active edge of `ckref' (master clock) that samples incoming YCrCb data (Refer to Functional Description, Section IV.17). 0 `ckref' rising edge (e.g. data with OSD coming from STi3520M) 1 `ckref' falling edge (e.g. data without OSD coming from STi3520M)
Note : Typically, this bit is used when two STV0119A's are used in a `dual encoding' configuration.
del[2:0]
(*)
Delay on luma path with reference to chroma path (Refer to Functional Description, Section IV.9) del2 del1 del0 Delay on luma path with reference to chroma path (one pixel corresponds to 1/13.5MHz (74.04ns)) 0 1 0 + 2 pixel delay on luma 0 0 1 + 1 pixel delay on luma 0 0 0 + 0 pixel delay on luma 1 1 1 - 1 pixel delay on luma 1 1 0 - 2 pixel delay on luma Other + 0 pixel delay on luma
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_4 - Configuration4
MSB Content Default syncin_ad1 0 syncin_ad0 0 syncout_ad1 syncout_ad0 0 0 aline 0 txdl2 0 txdl1 0 LSB txdl0 0
syncin_ad
(*)
Adjustment of incoming sync signals (Refer to Functional Description, Section IV.5). Used to insure correct interpretation of incoming video samples as Y, Cr or Cb when the encoderis slavedto incomingsync signals(incl. `F/H'flagsstripped offITU-R656/D1 data). syncin_ad1 syncin_ad0 Internal delay undergone by incoming sync 0 0 Nominal 0 1 +1 ckref 1 0 +2 ckref 1 1 +3 ckref
syncout_ad Adjustment of outgoing sync signals (Refer to Functional Description, SectionIV.4). Used to insure correct interpretation of incoming video samples as Y, Cr or Cb when the encoder is master and supplies sync signals. syncout_ad1 syncout_ad0 Delay added to sync signals before they are output (*) 0 0 Nominal 0 1 +1 ckref 1 0 +2 ckref 1 1 +3 ckref aline (*) txdl[2:0] Video active line duration control(Refer to Functional Description, Section IV.2) 0 Full digital video line encoding (720 pixels - 1440 clock cycles) 1 Active line duration follows ITU-R/SMPTE `analog' standard requirements Teletext data latency (* "000" default) (Refer to Functional Description, Section IV.15) th The encoder will clock in the first Teletext data sample on the (2+txdl[2:0]) rising edge of the master clock following the rising edge of TTXS (Teletext Synchro signal, supplied by the encoder).
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_5 - Configuration5
MSB Content Default rgb_nyc 0 bkcvbs1 0 reserved 1 reserved 1 bk_ys 0 bk_c 0 bk_cvbs 0 LSB dacinv 0
rgb_nyc (*) bkcvbs1 (*) bk_ys (*) bk_c (*) bk_cvbs (*) dacinv (*)
Selection between RGB or S-VHS/CVBS outputs present on DACs (refer to Functional Description, Section IV.12) 0 Y - C - CVBS - CVBS1 on DACs 1 R - G - B - CVBS1 on DACs Blanking of DAC CVBS 0 DAC CVBS in normal operation 1 DAC input code forced to blanking level Blanking of DAC G/Y' 0 DAC G/Y in normal operation 1 DAC input code forced to black level (if G) or blanking level (if Y) Blanking of DAC `R/C' 0 DAC R/C in normal operation 1 DAC input code forced to black level (if R) or neutral level [no color] (if C) Blanking of DAC `B/CVBS' 0 DAC B/CVBS in normal operation 1 DAC input code forced to black level (if B) or blanking level (if CVBS) `Inverts' DAC codes to compensate for an inverting output stage in the application 0 DAC non inverted inputs 1 DAC inverted inputs
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_6 - Configuration6
MSB Content Default softreset 0 jump 0 dec_ninc 0 free_jump 1 xxxx 0 xxxx 0 chgi2c 0 LSB maxdyn 0
softreset (*)
Software reset 0 No reset 1 Software reset
Note : Bit `softreset' is automatically reset after internal reset generation. Software reset is active during 4 CKREF periods. When softreset is activated, all the device is reset as with hardware reset except for the first six user registers (configurations) and for registers 10 up to 14 (increment and phase of oscillator), 31-33, 34-37 and 39-42.
jump, dec_ninc, free_jump jump dec_ninc free_jump 0 0 0 Normal mode (no line skip/insert capability) CCIR : 313/312 or 263/262 non-interlaced : 312/312 or 262/262 0 x 1 Manual mode for line insert ("dec_ninc" = 0) or skip ("dec_ninc" = 1) capability. Both fields of all the frames following the I2C writing are modified accordingto "lref"and "ltarg"bits of registers21-22-23 (by default, "lref" = 0 and "ltarg"= 1 which leads to normal mode above). 1 0 0 Automatic line insert mode. nd 2 The 2 field of the frame following the I C writing is increased. Line insertion is done after line 245 in 525/60 and after line 330 in 625/50. "lref" and "ltarg" bits are ignored. 1 1 0 Automatic line skip mode. The2nd field of the framefollowing the I2C writtingis decreased. Line suppression is done after line 245 in 525/60 and after line 330 in 625/50. "lref" and "ltarg" bits are ignored. 1 x 1 Not be used
Notes : - Refer to Functional Description (Section IV.18) - bit "jump" is automatically reset after use.
chgi2c (*)
Chip address selection 0 Chip address : write = 40hex ; read = 41hex 1 Chip address : write = 42hex; read = 43hex
Note : Setting this bit to 1 changes the chip address provided that pin ttxs/csi2c is tied to Vdd when the 0-to-1 transition occurs. Refer to sections IV.16 and IV.17. The new address is valid until the next hardware reset.
maxdyn (*)
Max dynamic magnitude allowed on YCrCb inputs for encoding (Refer to Functional Description, Section IV.6). 0 10hex to EBhex for Y, 10hex to E0hex for chrominance (Cr,Cb) 1 01hex to FEhex for Y, Cr and Cb
Note : In any case, EAV and SAV words are replaced by blanking values before being fed to the luminance and chrominace processings
REGISTER_7 and 8 : Reserved
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_9 - Status (read only)
MSB Content hok atfr buf2_free buf1_free fieldct2 fieldct1 fieldct0 LSB jumping
hok (*) atfr (*) buf2_free
Hamming decoding of frame sync flag embedded within ITU-R656/D1 compliant YCrCb streams. 0 Consecutive errors 1 A single or no error
Note : signal quality detector is issued from Hamming decoding of EAV,SAVfrom YCrCb
Frame synchronization flag (slave mode only) 0 Encoder not synchronized 1 Encoder synchronized Closed caption registers access condition for field 2 (refer to Functional Description, Section IV.13) Closed caption data for field 2 is buffered before being output on the relevant TV line; buf2_free is reset if the buffer is temporarily unavailable. If the microcontroller can guaranteethat registers 41 and 42 (cccf2) are never written more than once between two frame reference signals, then bit `buf2_free' will always be true (set). Otherwise, closed caption field2 registers access might be temporarily forbidden by resetting bit `buf2_free' until the next field2 closed caption line occurs. Note that this bit is false (reset) when 2 pairs of data bytes are awaiting to be encoded, and is set back immediately after one of these pairs has been encoded (so at that time,encoding of the last pair of bytes is still pending) Reset value = 1 (access authorized) Closed caption registers access condition for field 1 Same as buf2_free but concerns field 1. Reset value = 1 (access authorized)
(*) buf1_free (*)
fieldct[2:0] Digital field identification number 000 Indicates field 1 ... 111 Indicates field 8 fieldct[0] also represents the odd/even information (odd='0', even='1') jumping (*) Indicates whether a frame length modification has been programmed at `1' from programming of bit `jump' to end of frame(s) concerned. Default = 0 Refer to register 6 and registers 21-22-23.
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTERS_10_11_12- Increment_dfs : Increment for digital frequency synthesizer
MSB register_10 register_11 register_12 d23 d15 d7 d22 d14 d6 d21 d13 d5 d20 d12 d4 d19 d11 d3 d18 d10 d2 d17 d9 d1 LSB d16 d8 d0
These registers contain the 24-bit increment used by the DDFS if bit `selrst' equals `1' to generate the frequencyof the subcarrieri.e. the address that is supplied to the sineROM. It thereforeallows to customize the subcarrier frequency synthesized. Refer to Functional Description, Section IV.7. 1 LSB ~ 1.6 Hz The procedure to validate usage of these registers instead of the hard-wired values is the following : - Load the registers with the required value - Set bit `selrst' to 1 (Reg 2) - Perform a software reset (Reg 6) Notes : The values loaded in Reg10-11-12 are taken into account after a software reset, and ONLY IF bit `selrst'='1' (Reg. 2) These registers are never reset and must be explicitly written into to contain sensible information. On hardware reset (=> `selrst'=0) or on soft reset with selrst='0', the DDFS is initalized with a hardwired increment, independent of Registers 10-12. These hardwired values being out of any user register these cannot be read out of the STV0119A. These values are : Value Frequency Synthesized Ref.Clock d[23:0] : 21F07C hexa for NTSC M (*) f = 3.5795452MHz 27MHz d[23:0] : 2A098B hexa for PAL BGHIN f = 4.43361875MHz 27MHz d[23:0] : 21F694 hexa for PAL N f = 3.5820558MHz 27MHz d[23:0] : 21E6F0 hexa for PAL M f = 3.57561149MHz 27MHz `NTSC-4.43' can be obtained with d[23:0] value like for PALBGHI but with standardfixed as NTSC.
REGISTERS_13_14 - Phase_dfs : Static phase offset for digital frequency synthesizer (10 bits only)
MSB register_13 register_14 o21 o20 o19 o18 o17 o16 o23 o15 LSB o22 o14
Under certain circumstances (detailed below), these registers contain the 10 MSBs of the value with which the phase accumulator of the DDFS is initialized after a 0-to-1 transition of bit `rstosc' (Reg 2), or after a standard change, or when cyclic phase readjustment has been programmed (see bits valrst[1:0] of Reg 2). The 14 remaining LSBs loaded into the accumulator in these cases are all `0's (this allows to define the phase reset value with a 0.35accuracy). The procedure to validate usage of these registers instead of the hard-wired values is the following : - Load the registers with the required value - Set bit `selrst' to 1 (Reg 2) - Perform a software reset (Reg 6) Notes : Registers 13-14 are never reset and must be explicitly written into to contain sensible information. If bit `selrst'=0 (e.g. after a hardware reset) the phase offset used to reinitialize the DDFS is the hard-wired value. The hard-wired values being out of any register, they cannot be read out of the STV0119A. These are : - D9C000hex for PAL BDGHI, N, M - 1FC000hex for NTSC-M
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_15 : Reserved REGISTER_16 : Reserved REGISTER_17 : chipID (read only) : STV0119AIdentification Number 0 1 1 1 0 1 1 1 (codes 119 in binary format) REGISTER_18 : revID (read only) : STV0119A Revision Number 0 0 0 0 0 0 1 1 (for third revision) REGISTER_19 : Reserved REGISTER_20 : Reserved REGISTERS_21_22_23: line_reg = ltarg[8:0] and lref[8:0]
MSB register_21 register_22 register_23 ltarg8 ltarg0 lref1 ltarg7 lref8 lref0 ltarg6 lref7 ltarg5 lref6 ltarg4 lref5 ltarg3 lref4 ltarg2 lref3 LSB ltarg1 lref2 -
These registers may be used to jump from a reference line (end of that line) to the beginning of a target line of the SAME FIELD. However, not all lines can be skipped or repeated with no problem and, if needed, this functionality has to BE USED WITH CAUTION. lref[8:0] contains in binary format the reference line from which a jump is required. ltarg[8:0] contains the target line binary number. Default values: lref[8:0] = 000000000 and ltarg[8:0] = 000000001
REGISTER_31-32-33 - cgms_bit[1:20] : CGMS Data registers (20 bits only)
MSB register_31 register_32 register_33 b5 b13 b6 b14 b7 b15 b8 b16 b1 b9 b17 b2 b10 b18 b3 b11 b19 LSB b4 b12 b20
These registers are never reset. Word0A => bit1....bit3 Word0B => bit4....bit6 Word1 => bit7....bit10 Word2 => bit11....bit14 CRC => bit15...bit20(not internally computed) Refer to Functional Description, Section IV.14
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_34-35-36-37 - ttx_block_[1:4]_def. : Teletext Block Definition (Refer to Functional Description, Section IV.15)
MSB register_34 txbd1 register_35 txbd2 register_36 txbd3 register_37 txbd4 txbs1.3 txbs2.3 txbs3.3 txbs4.3 txbs1.2 txbs2.2 txbs3.2 txbs4.2 txbs1.1 txbs2.1 txbs3.1 txbs4.1 txbs1.0 txbs2.0 txbs3.0 txbs4.0 txbe1.3 txbe2.3 txbe3.3 txbe4.3 txbe1.2 txbe2.2 txbe3.2 txbe4.2 txbe1.1 txbe2.1 txbe3.1 txbe4.1 LSB txbe1.0 txbe2.0 txbe3.0 txbe4.0
These are four Teletext Block Definition registers, used in conjunctionwith Reg 38 (TeletextBlock Mapping). Each of these registers defines a start line (TXBSx[3:0]) and an end line (TXBEx[3:0]). [TXBSx = Teletext Block Start for block x, TXBEx = Teletext Block End for block x] When applying to field1 : TXBSx[3:0]=0 codes line 7, ... TXBSx[3:0]=i codes line 7+i, ... TXBSx[3:0]=15dec (`1111'bin) codes line 7+15=22 When applying to field2 : TXBSx[3:0]=0 codes line 320, ... TXBSx[3:0]=i codes line 320+i, ... TXBSx[3:0]=15dec (`1111'bin) codes line 320+15=335 (ITU-R601/625 line numbering) DEFAULT value: none, registers 34-37 are never reset.
REGISTER_38 - ttx_block_map : Teletext Block Mapping
MSB register_38 txmf1.1 txmf1.2 txmf1.3 txmf1.4 txmf2.1 txmf2.2 txmf2.3 LSB txmf2.4
(txmf1 stands for 'Teletext Block Mapping to field1, txmf2 stands for 'Teletext Block Mapping to field2) This register allows to map the blocks of Teletext lines defined by registers 34 to 37 to either field1, field2 or both : Its default value is "00000000" txmf1.N defines whether txbdN (Nth teletext block, see reg34-37 above) applies to field 1, txmf2.N defines whether txbdN (Nth teletext block, see reg34-37 above) applies to field 2. In other words, if txmf1.N=1 then Teletext will be encoded in field 1 from the line defined by txbsN.[3:0] (see above) to the line defined by txbeN.[3:0]. Similarly, if txmf2.N=1 then Teletext will be encoded in field 2 from the line defined txbsN.[3:0] (see above) to the line defined by txbeN.[3:0].
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_39-40 - cccf1 : Closed caption characters/extended data for field 1 First byte to encode in field1 :
register_39 MSB opc11 c117 c116 c115 c114 c113 c112 LSB c111
opc11
Odd-parity bit of US-ASCII 7-bit character c11[7:1]
MSB opc12 LSB c121
Second byte to encode in field1:
register_40 c127 c126 c125 c124 c123 c122
opc12
Odd-parity bit of US-ASCII 7-bit character c12[7:1] Default value : none, but closed captions enabling without loading these registers will issue character NULL. Registers 39-40 are never reset.
REGISTER_41-42 : cccf2 : Closed caption characters/extended data for field 2 First byte to encode in filed2 :
register_41 MSB opc21 c217 c216 c215 c214 c213 c212 LSB c211
opc21
Odd-parity bit of US-ASCII 7-bit character c21[7:1]
MSB opc22 LSB c221
Second byte to encode in field2 :
register_42 c227 c226 c225 c224 c223 c222
opc22
Odd-parity bit of US-ASCII 7-bit character c22[7:1] Default value : none but closed captions enabling without loading these registers will issue character NULL. Registers 41-42 are never reset.
REGISTER_43 - cclif1 : Closed caption/extended data line insertion for field 1 TV line number where closed caption/extended data is to be encoded in field 1 is programmable through the following register :
register_43 Default MSB xxxx 0 xxxx 0 xxxx 0 l1_4 0 l1_3 1 l1_2 1 l1_1 1 LSB l1_0 1
- 525/60 system : (525-SMPTE line number convention) Only lines 10 through 22 should be used for closed caption or extended data services (line 1 through 9 contain the vertical sync pulses with equalizing pulses). l1[4:0] = 00000 no line selected for closed caption encoding l1[4:0] = 000xx do not use these codes ... l1[4:0] = i code line (i+6) (SMPTE) selected for encoding ... l1[4:0] = 11111 line 37 (SMPTE) selected - 625/50 system: (625-CCIR/ITU-R line number convention) Only lines 7 through 23 should be used for closed caption or extended data services. l1[4:0] = 00000 no line selected for closed caption encoding ... l1[4:0] = i code line (i+6) (CCIR) selected for encoding (i > 0) ... l1[4:0] = 11111 line 37 (CCIR) selected (*) Default value = 01111 line 21 (525/60, 525-SMPTE line number convention). This value also corresponds to line 21 in l625/50 system,(625-CCIR line number convention).
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STV0119A
VI - REGISTERS (continued) VI.2 - Register Contents and Description (continued) (*) = DEFAULT mode when NRESET pin is active (LOW level)
REGISTER_44 - cclif2 : Closed caption/extended data line insertion for field 2 TV line number where closed caption/extended data is to be encoded in field 2 is programmable through the following register :
MSB register_44 Default xxxx 0 xxxx 0 xxxx 0 I2_4 0 I2_3 1 I2_2 1 I2_1 1 LSB I2_0 1
- 525/60 system : (525-SMPTE line number convention) Only lines 273 through 284 should be used for closed caption or extended data services (preceding lines contain the vertical sync pulses with equalizing pulses), although it is possible to program over a wider range. l2[4:0] = 00000 no line selected for closed caption encoding l2[4:0] = 000xx do not use these codes l2[4:0] = i line (269 +i) (SMPTE) selected for encoding ... l2[4:0] = 01111 line 284 (SMPTE) selected for encoding l2[4:0] = 11111 line 300 (SMPTE) Note : if cgms is allowed on lines 20 and 283 (525/60, 525-SMPTE line number convention), closed captions should not be programmed on these lines. - 625/50 system : (625-CCIR line number convention) Only lines 319 through 336 should be used for closed caption or extended data services (preceding lines contain the vertical sync pulses with equalizing pulses), although it is possible to program over a wider range. l2[4:0] = 00000 no line selected for closed caption encoding (i > 0) l2[4:0] = i line (318 +i) (CCIR) selected for encoding ... l2[4:0] = 10010 line 336 (CCIR) selected for encoding l2[4:0] = 11111 line 349 (CCIR) (*) Default value = 01111 line 284 (525/60, 525-SMPTE line number convention). This value also corresponds to line 333 in 625/50 system, (625-CCIR line number convention).
REGISTERS_45 up to 63 : Reserved
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VDD
10F 100nF
CKREF = 27MHz 22k VDD VDD 22F
VII - APPLICATION
ODD/EVEN 21 NRESET 4.7k 4.7k SDA SCL VSS 10 CKREF 24 TTXD 23 TTXS/CSI2C 75 VIDEO OUTPUT STAGE 75 VIDEO OUTPUT STAGE 75 VIDEO OUTPUT STAGE VR_RGB 17 CHROMA PROCESSOR 9-BIT DAC 6.8nF VDDB I REF(RGB) 16 VDDA 15 100nF 1.1k 47k TRANSPORT IC (ST20)
28
VDD
HSYNC 1 25
SYNC CONTROL & VIDEO TIMING GENERATOR CTRL + CFG REGISTER 26 27
Y/CR/CB7
2
Figure 34 : Typical Application
Y/CR/CB6
3
Y/CR/CB5
4
AUTOTEST COLOR BAR PATTERN
MPEG DECODER
Y/CR/CB4 5
DEMULTIPLEXER CB-CR RGB ENCODING 22 G/Y
Y/CR/CB3
6
TELETEXT
Y/CR/CB2
7
Y/CR/CB1 Y 9 19 R/C LUMA PROCESSING
8
20
Y/CR/CB0
75 MACROVISION 7.0/6.1 18 TRAP CLOSED CAPTIONS CGMS
VR_CVBS
12
1.2k
VSSA
14
VDDA = 3.3V
STV0119A (Master)
VDDA 10F
10F IN 200 2.2k F 75 OUT
VDDB = 5V
VDD = 3.3V
= VSSA(0V)
= VSS(0V) VIDEO OUTPUT STAGE F : Low Pass Filter
820
20
IREF(CVBS)
13
9-BIT TRIDAC
6.8nF
SWITCH
VIDEO OUTPUT STAGE
CVBS
11
B/CVBS
STV0119A
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0119A-03.EPS
STV0119A
VIII - PACKAGE MECHANICAL DATA 28 PINS - PLASTIC MICROPACKAGE (SO)
Dimensions A a1 b b1 C c1 D E e e3 F L S
Min. 0.1 0.35 0.23
Millimeters Typ.
Max. 2.65 0.2 0.49 0.32 45 (Typ.)
o
Min. 0.004 0.014 0.009
Inches Typ.
Max. 0.104 0.0078 0.019 0.013
0.5 17.7 10 1.27 16.51 7.4 0.4 7.6 1.27 8o (Max.) 0.291 0.016 18.1 10.65 0.697 0.394
0.020 0.713 0.419 0.050 0.65
SO28C.TBL
0.299 0.050
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical comp onents in lifesupport devicesor systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved Purchase of I C Components of STMicroelectronics, conveys a license under the Philips I C Patent. Rights to use these components in a I 2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco- The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
2 2
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PM-SO28.EPS

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